The present invention relates generally to buffers and more specifically to an improved CMOS output buffer.
CMOS buffers generally include a pair of complementary MOS transistors having a conduction path connected in series between a pair of power terminals and the output being at the junction of the two transistors. The output transistors act as a current source or sink and must drive a generally capacitive load. Using this structure, the current available during switching typically is continuously changing. The maximum current occurs when the device is in its saturated region, once in the linear range the control current decreases as the voltage across the output device decreases. This change in output current requires a higher peak current than if the device delivered a constant current for the same switching time.
An effort to increase the speed of switching while dissipating less power and providing symmetrical rise and falls has been addressed in level shifting circuits as illustrated in U.S. Pat. No. 4,450,371 to Bismarck. A large device capable of carrying a lot of current is switched on at the beginning of the transition to quickly supply current to the output and is then switched off as the output approaches the appropriate output level. These devices are in parallel with smaller high-ON-impedance load devices.
One method of stabilizing the maximum output current that we initially derived is to convert the simple output inverter structure into switched current sources as illustrated in FIG. 1. Transistors Q1 and Q3 and transistors Q2 and Q4 form current mirrors with the output devices Q1 and Q2 being the output leg of the current mirrors. The problem with the current source approach of FIG. 1 is that as the output voltage VO approaches either of the power terminals V+ or ground, the power in the output transistors Q1 and Q2 approach zero. However, an internal DC power still occurs.
The object of the present invention is to operate the output transistor at a controlled current capacity during switching without an accompanying power dissipation at steady state.
This and other objects of the invention are attained by controlling the output transistor of the buffer to operate in a constant current mode in response to an input signal transition of the buffer and subsequently operating the output transistor in a constant voltage mode when the output signal approaches the desired output level. The output transistor is controlled by limiting the voltage applied to its gate until the output signal approaches a desired output voltage, then the maximum supply voltage is applied to the gate. The voltage limiting can be provided by either a voltage divider or using the output transistor as the output leg of a current mirror which is activated by the input signal transition to drive the output transistor in a constant current mode and deactivated by the output signal approaching the desired output level.
The voltage divider limits the gate-to-source voltage and thereby drives the output transistor in a saturated mode. Once the output reaches a desired level, the voltage divider is disabled and a constant voltage is applied to the gate to drive the output transistor in its linear region. The voltage divider may include a resistor and series connected switch responsive to input signal to activate the voltage divider and a second resistance/switch which is controlled by the output signal to perform the activation and deactivation of the voltage divider.
In the current mirror embodiment a switchable current source is responsive to the input signal transition to provide an input current to the current mirror and includes a series switch in the input leg to disconnect the input leg from a power terminal to disrupt the current source and drive the output transistor with a constant voltage.
In response to an opposite input signal transition, the two ends of the voltage divider or the input leg of the current mirror are connected to the same power terminals to prevent drive of the output transistor. An additional switching element may be provided directly to the control gate of the output transistor and being responsive to the input signal to quickly turn the output transistor off.
The buffer may have a complementary pair of output devices each being responsive to an opposite transition so as to be operated in a constant current mode during the initial stage and in a constant voltage mode as the output approaches a desired output level. Interconnecting logic may be provided to prevent activation of one of the output transistors until the other has been turned off. Input latches and tri-state control may also be provided as part of the input logic.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.